library ieee;
use ieee.std_logic_1164.all;

entity AND_ent_2 is
port( x0: in std_logic;
x1: in std_logic;
F: out std_logic);
end AND_ent_2;

architecture behav of AND_ent_2 is
begin
F<=x0 and x1;
end behav;
library ieee;
use ieee.std_logic_1164.all;

entity AND_ent_2 is
port( x0: in std_logic;
x1: in std_logic;
F: out std_logic);
end AND_ent_2;

architecture behav of AND_ent_2 is
begin
F<=x0 and x1;
end behav;
library ieee;
use ieee.std_logic_1164.all;

entity AND_ent_2 is
port( x0: in std_logic;
x1: in std_logic;
F: out std_logic);
end AND_ent_2;

architecture behav of AND_ent_2 is
begin
F<=x0 and x1;
end behav;
library ieee;
use ieee.std_logic_1164.all;

entity AND_ent_2 is
port( x0: in std_logic;
x1: in std_logic;
F: out std_logic);
end AND_ent_2;

architecture behav of AND_ent_2 is
begin
F<=x0 and x1;
end behav;
