library IEEE
use IEEE.STD_LOGIC_1164.ALL;

entity main is
end main;

architecture struct of main is
	signal temp0,temp1308839391,temp-1483795394,temp972564956,temp972564956,temp-1483795394,temp1308839391: std_logic;begin
comp_0 : entity AND_ent_2 port map (temp1308839391,temp-1483795394,temp972564956)
comp_1 : entity AND_ent_2 port map (temp972564956,temp-1483795394,temp1308839391)
end struct;